1. Technical Field of the Invention
The present invention relates to a programmable logic LSI such as a field programmable gate array (FPGA), wherein element cells are used either for logic function or for wiring function such as a cross bar switch.
2. Description of the Prior Art
The programmable logic LSI such as FPGA is an LSI for implementing a hardware, according to configuration information stored in the LSI itself. As the scale of hardware becomes enlarged, Gate arrays are being replaced by programmable logic LSI such as FPGA. In general, the programmable logic LSI comprises logic cells, wiring cells, and input/output cells. There is disclosed, in JP appl.no.10-309285 (1998), a programmable logic LSI which integrates the logic cell and wiring cell in order to change freely a ratio of wiring resources to logic resources, although concrete method for constructing the cells is not disclosed.
It is necessary to fix the connections between the input/output terminals of the cells, when a plurality of cells for programmable logic means are assembled.
The first measure is to heighten a degree of freedom for selecting the locations of input/output terminals of each cell, and to assure the input/output terminals for sequenced cells. The second measure is to insert programmable wiring cell between programmable logic cells. Further, the third measure is to assure the input/output terminals for sequenced cells, by constructing an LSI which comprises a plurality of cells of which input/output locations are different from each other.
In JP 9-148440A (1997), variable logic blocks and switch matrices are arranged in a checker flag pattern, wherein connection wiring region is provided on the variable logic blocks by applying multi-layer wiring technique, whereby the area of the switching matrices among the logic blocks is reduced and the chip size is also reduced. Further, signal delay is reduced, because the number of switches on the connection lines between the logic blocks is reduced.
However, the circuit scale in each cell is increased, when adopting the first measure as mentioned-above. Further, cell number is increased, when adopting the second measure as mentioned-above. Furthermore, when adopting the third measure as mentioned above, the hardware becomes complicated, because various types of cells must be used.
Further, the conventional programmable logic LSI as disclosed in the above-mentioned Japanese Patent Application No. 10-309285 (1998) has a disadvantage that the resources are not fully utilized, because the wiring resource is not utilized, when the LSI is utilized as a programmable logic means. Furthermore, it has another disadvantage that the wiring resource is apt to become floated, when the wiring resource is not utilized.
Therefore, an object of the present invention is to simplify the hardware construction by using cells which is an array of element circuits.
Another object of the present invention is to increase cells for programmable logic means and memory means, without increasing the circuit scale of each cell. In other words, the object of the invention is to decrease the programmable wiring means.
Still another object of the present invention is to suppress an overhead and to prevent an occurrence of floating state on the wiring means which are not operating.
The programmable logic LSI includes a two dimensional array of element cells which functions as programmable wiring means, programmable logic means and memory means. Each of the element cells comprises a plurality of inter-cell connection control circuits for controlling connections between the element cells, and a logic/wiring integration circuit for operating as a cross-bar switch as the wiring means and for inputting and outputting logic signals as the logic means and the memory means. The logic/wiring integration circuit comprises memory circuits for storing the logic signals, read-out circuits for reading out the logic signals, and switches for switching on and off the connections between the element cells.
Each of the element cells may include a write circuit for writing the logic signals.
In the programmable logic LSI of the present invention, element cells as many as required are used as logic means or wiring means.
According to the present invention, a programmable logic LSI which integrates programmable logic means, and programmable wiring means and memory means can be implemented by a two- dimensional array of element cells.
Further, according to the present invention, a degree of freedom of connecting the programmable logic cells with each other becomes high, because the connections in the element cell can be devised variously, and a logic element cell can function as a wiring element cell. Therefore, the element cells are utilized efficiently, because a number of wiring element cells can be suppressed, when more logic element cells are required.
Furthermore, according to the present invention, the floating state on the connection lines can be avoided, because the signal value on the connection lines are latched on the basis of the value stored in the memory means.